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74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26 Series Resistors in Outputs
September 2001 Revised February 2002
74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26 Series Resistors in Outputs
General Description
The ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Outputs (On) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The ALVC162835 is designed with 26 series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74ALVC162835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74ALVC162835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s Compatible with PC100 DIMM module specifications s 1.65V to 3.6V VCC specifications provided s 3.6V tolerant inputs and outputs s 26 series resistors in outputs s tPD (CLK to O n) 5.4 ns max for 3.0V to 3.6V VCC 6.3 ns max for 2.3V to 2.7V VCC 9.2 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model >200V
Note 1: To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pulldown resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver.
Ordering Code:
Order Number 74ALVC162835T Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2002 Fairchild Semiconductor Corporation
DS500646
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74ALVC162835
Connection Diagram
Pin Descriptions
Pin Names OE LE CLK I1 - I18 O1 - O18 Description Output Enable Input (Active LOW) Latch Enable Input Clock Input Data Inputs 3-STATE Outputs
Truth Table
Inputs OE H L L L L L L LE X H H L L L L CLK X X X In X L H L H X X Outputs On Z L H L H O0 (Note 2) O0 (Note 3)

H L
H = Logic HIGH L = Logic LOW X = Don't Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition Note 2: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 3: Output level before the indicated steady-state input conditions were established.
Logic Diagram
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74ALVC162835
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 5) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or Ground Current per Supply Pin (ICC or Ground) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to +4.6V -0.5V to VCC + 0.5V -50 mA -50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 6)
Power Supply Operating Input Voltage Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 4: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
-40C to +85C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = -100 A IOH = -2 mA IOH = -4 mA IOH = -6 mA IOH = -8 mA IOH = -12 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II IOZ ICC ICC Input Leakage Current 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 0 VI 3.6V 0 VO 3.6V VI = V CC or GND, IO = 0 VIH = VCC - 0.6V 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3.0 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3 3.6 3.6 3.6 3 - 3.6 VCC - 0.2 1.2 1.9 1.7 2.4 2 2 0.2 0.45 0.4 0.55 0.55 0.6 0.8 5.0 10 40 750 A A A A V V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 V V Max Units
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74ALVC162835
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter CL = 50 pF VCC = 3.3V 0.3V Min fCLOCK tW tS Clock Frequency Pulse Width LE High CLK High or Low Setup Time Data Before CLK Data Before CLK CLK High CLK Low tH Hold Time Data After CLK Data After LE fMAX Maximum Clock Frequency Delay LE to O CLK to O tPZL, tPZH Output Enable Time tPLZ, tPHZ Output Disable Time CLK High or Low tPHL, tPLH Propagation I to O 3.3 3.3 1.7 1.5 1.0 0.7 1.4 150 1.0 1.3 1.4 1.1 1.3 4.2 5.1 5.4 5.5 4.5 Max 150 3.3 3.3 2.1 1.6 1.1 0.6 1.7 150 5.0 5.8 6.1 6.5 4.9 VCC = 2.7V Min Max 150 3.3 3.3 2.2 1.9 1.3 0.6 1.4 150 1.0 1.3 1.4 1.4 1.0 5.0 5.9 6.3 6.3 4.9 100 1.5 1.5 2.0 1.5 1.5 9.8 9.8 9.2 9.8 7.9 ns ns ns 1.0 ns MHz CL = 30 pF VCC = 2.5V 0.2V VCC = 1.8V 0.15V Min Max 150 4.0 4.0 2.5 ns Min Max 100 MHz ns Units
AC Electrical Characteristics Over Load (Note 7)
RL = 500, VCC = 3.3V 0.15V Symbol Parameter TA = -0C to +85C CL = 0 pF Min tPHL, tPLH tPHL, tPLH Propagation Delay Bus to Bus Propagation Delay Clock to Bus 0.9 1.4 Max 2.0 2.9 Min 1.0 1.9 TA = -0C to +65C CL = 50 pF Max 4.0 5.0 ns ns Units
Note 7: Characterized only.
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Parameter Control Data VI = 0V or VCC VI = 0V or VCC VI = 0V, or VCC Conditions TA = +25C VCC 3.3 3.3 3.3 3.3 2.5 Outputs Disabled f = 10 MHz, CL = 0 pF 3.3 2.5 Typical 3.5 5 7 40 35 14 125 pF Units
pF pF
Power Dissipation Capacitance Outputs Enabled f = 10 MHz, CL = 0 pF
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74ALVC162835
IOUT - VOUT Characteristics
IOH versus VOH
FIGURE 1. Characteristics for Output - Pull Up Drive
IOL versus VOL
FIGURE 2. Characteristics for Output - Pull Down Driver
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74ALVC162835
AC Loading and Waveforms
TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 3. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50) Symbol Vmi Vmo Vx Vy VL VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2 1.8 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2
FIGURE 4. Waveform for Inverting and Non-inverting Functions tr = tf 2.0ns, 10% to 90%
FIGURE 5. 3-STATE Output High Enable and Disable Times for Low Voltage Logic tr = tf 2.0ns, 10% to 90%
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic tr = tf 2.0ns, 10% to 90%
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74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26 Series Resistors in Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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